In the manufacturing of integrated circuits, silicon-containing layers, such as silicon dioxide, silicon nitride, polysilicon, metal silicide, and monocrystalline silicon layers, which are formed on a substrate, and etched to form gates, vias, contact holes, trenches, and/or interconnect lines. In the etching process, a patterned mask layer comprising silicon dioxide, silicon nitride, and/or photoresist, is formed on the substrate using conventional methods, and the exposed portions of the silicon-containing layers on the substrate are etched by microwave or RF energized process gas.
One problem with conventional etching processes arises because it is difficult to etch a surface layer comprising two or more compositionally different regions at the same etch rate. For example, compositionally variant surface layers occur in p-channel and n-channel CMOS transistors fabricated in symmetrical matched pairs, to operate at lower voltages and faster operating speeds. As illustrated in FIG. 1a, a set of matched transistors 10a,b comprises adjacent regions in the semiconductor substrate 45 doped with a dopant, such as boron or phosphorous, to form a p-well 12a and a n-well 12b. Discrete regions of the p-well 12a and n-well 12b are implanted to define the source 16 and drain 18 of the transistors 10a,b. Next, the surface of the substrate 45 overlying the boundary of the p-well 12a and n-well 12b is etched using conventional photolithographic and etching techniques to open a void for an isolation structure 22. A layer of SiO.sub.2 is formed on the surface of the substrate 45, to create the isolation structure 22 and an overlying gate oxide layer 175. As shown in FIG. 1b, a layer of polysilicon 170 is grown over the gate oxide layer 175, and doped with different types of dopant, i.e., n-type or p-type, and different concentrations of dopants to form a gate structure 28a,b for each transistor 10a,b. A patterned mask layer 195 is then deposited on the polysilicon layer and it is etched to form the dual gate structures 28a,b, shown in FIG. 1a.
When conventional etching processes are used to etch these types of dual doped polysilicon layers 170, the different regions 180a, 180b are etched at different etch rates. For example, the regions with n-type dopant 180a are typically etched as much as 20% faster than the regions 180b with p-type dopant. Also, doped regions are typically etched at much faster rates than undoped regions, or regions in which the implant has not been diffused or activated by annealing the substrate. This difference in etch rates can lead to residues depositing in the more slowly etched regions and/or excess gate oxide 175 loss in the more rapidly etched regions. Furthermore, conventional etching processes also etch features having unacceptably large variations in profile angles (more than 3 degrees) from one region to another region on the substrate 45. The profile angle is the angle made by a sidewall of the etched features with the plane of the substrate. It is desirable to have an etching process that etches through the compositional variant regions at the substrate surface with uniform etching rates and little or no variations in profile angles of etched features.
In one solution, highly chemically reactive etchant gases are used to etch through layers having varying concentration or composition of dopants at a faster and more uniform etch rates. However, the highly reactive etching gas typically provides little or no etching selectivity relative to the resist layer or underlayer, and typically etches through the underlying layer at the same high etch rate. This is particularly common when the underlayer also contains elemental silicon or silicon compounds. For example, when etching through a polysilicon layer that overlies a thin silicon dioxide gate oxide layer, it is necessary to stop the etching process without etching through the underlayer. Thus there is a need for an etching process gas that provides high and uniform etch rates for compositional variant regions in a polysilicon layer without sacrificing the etching selectivity to an underlayer which also contains silicon species.
Another problem arises because it is difficult to clean or remove the thin film of etchant residue that condenses and deposits on the internal surfaces of the chamber, such as the sidewalls, ceiling, and the surfaces of the internal components in the chamber, during the etching process. The composition of the etchant residue depends on the constituents of the process gas, the vaporized material being etched, and the mask layer on the substrate. For example, when tungsten silicide, polysilicon or other silicon-containing layers are etched, silicon-containing gaseous species are vaporized or sputtered to form a large component of the etchant residue deposits. In addition, the mask layer is also partially vaporized to form gaseous hydrocarbon or oxygen species which condense on the internal surfaces of the process chamber. Thus the etchant residue deposits are typically composed of polymeric byproducts containing hydrocarbon species vaporized from the photoresist in the mask layer, process gas species such as fluorine, chlorine, oxygen, or nitrogen; and vaporized silicon-containing species from the polysilicon layer being etched on the substrate. The chemical composition of the etchant residue deposits can also vary considerably across the chamber surface depending upon the composition of the local gaseous environment, the location of gas inlet and exhaust ports, and the geometry of the chamber.
The etchant residue deposits formed on the chamber surfaces are periodically cleaned to prevent contamination of the substrate 45. Typically, after processing of about 25 substrates, an in-situ plasma "dry-clean" process is used to dry clean the surfaces of the chamber. However, conventional cleaning plasmas that etch the etchant residue deposits contain highly energetic plasma species that rapidly erode the chamber walls and chamber components, and it is expensive to often replace such parts and components. Moreover, after processing of multiple substrates, the etching chamber is opened to the atmosphere and a "wet-cleaning" process is performed in which an operator uses an acid or solvent to scrub off and dissolve accumulated etchant residue deposits on the internal chamber surfaces. After the wet cleaning step, the chamber is "seasoned" by pumping down the chamber to a vacuum environment for 2 to 3 hours to allow moisture and other trapped volatile species to outgas. Thereafter, the etch process to be performed in the chamber, is run for 10 to 15 minutes on a series of dummy wafers until the chamber provides consistent and reproducible etching properties. In the competitive semiconductor industry, the increased cost per substrate and downtime of the chamber, during the dry cleaning, wet cleaning, and seasoning steps is highly undesirable. Also, the cleaning process often provides inconsistent and variable etching properties, because the wet cleaning process is manually performed by an operator.
Thus it is desirable to have an etching process that etches silicon-containing layers having different dopant concentrations at uniform etch rates, and with high etching selectivity to an underlayer. It is especially desirable for the etch process to etch polysilicon layers containing dual-doped or doped/undoped regions with uniform and consistent etch rates. It is also desirable for the etching process to clean-off etchant residue deposits formed on the internal surfaces of the chamber without excessive erosion of the chamber surfaces.